In this post i go through some questions – answers about Static RAM.
Feel free to ask more questions in comments.
What is Static RAM?
Static RAM is memory that the CPU has in its chip to store data and do faster calculations.
Isn’t normal RAM (DRAM) enough?
No, because DRAM is in a different chip and takes time travel to transfer data from DRAM to CPU.
So how SRAM works?
Data is transferred from DRAM to SRAM, the CPU does its work with the data in SRAM.
If the CPU wants more data that isn’t in SRAM, it asks for them from DRAM and then the data is moved from DRAM to SRAM.
Isn’t SRAM written in CPU description?
Yes, it is. It is mentioned as Cache.
The more SRAM(Cache) the better?
Yes, but this is 100% certain if we are talking about the same Cache Architecture.
Is there 1 SRAM(Cache) in CPU?
Every generation of CPUs changes the architecture of Cache.
You may have heard the terms L1 Cache, L2 Cache, L3 Cache.
L1 cache is smaller and fastest than all.
L2 cache is larger than L1 but slower.
L3 cache is larger than L2 but slower.
Note: This is like the standard but every generation of CPU changes the relationships between the Caches (If there are more than 1).
You should visit the manufacturer’s site for more details.
Why can’t there be only SRAM and not DRAM?
SRAM is way more expensive and occupies more space per unit than DRAM.
Is SRAM used in computers only?
No, it’s used almost in every electronic device with memory.
Is there 1 type of SRAM only?
No, there are plenty.
“Non-volatile SRAM (NV-SRAM)https://en.wikipedia.org/wiki/Static_random-access_memory
Non-volatile SRAMs, or nvSRAMs, have standard SRAM functionality, but they save the data when the power supply is lost, ensuring preservation of critical information. nvSRAMs are used in a wide range of situations – networking, aerospace, and medical, among many others – where the preservation of data is critical and where batteries are impractical. “
“Pseudo SRAM (PSRAM)https://en.wikipedia.org/wiki/Static_random-access_memory
PSRAMs have a DRAM storage core, combined with a self refresh circuit. They appear externally as a slower SRAM. They have a density/cost advantage over true SRAM, without the access complexity of DRAM. “
Asynchronous – independent of clock frequency; data in and data out are controlled by address transition
Synchronous – all timings are initiated by the clock edge(s). Address, data in and other control signals are associated with the clock signals “
If you have more questions, feel free to put it in the comments.